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st sitronix ST7063C 80ch segment driver for dot matrix lcd v1.3b 2005/11/08 1/12 n functions l dot matrix lcd driver with two 40 channel outputs l bias voltage (v1 ~ v4) l input/output signals n input : serial display data and control pulse from controller ic n output : 40 x 2 channels waveform for lcd driving n features l display driving bias : static to 1/5 l power supply for logic : 2.7v ~ 5.5v l power supply for lcd voltage (v dd ~v ee ) : 3v ~ 11v 100 pin qfp package and bare chip available n description ST7063C is a segment driver for dot matrix type lcd display. it features 80 channels with 40 x 2 bits bi-directional shift registers, data latches, lcd drivers and logic control circuits. it is fabricated by high voltage cmos process with low current consumption. the ST7063C can convert serial data received from an lcd controller, such as st7066u , into parallel data and send out lcd driving waveforms to the lcd panel. the ST7063C is designed for general purpose lcd drivers. it can drive both static and dynamic drive lcd. the lsi can be used as segment driver. the ST7063C has pin function compatibility with the ks0063(b) that allows the user to easily replace it with an ST7063C .
ST7063C v1.3b 2005/11/08 2/12 ST7063C specification revision history version date description 1.1 2000/07/31 first edition 1.2 2000/11/14 added qfp pad configuration(page 6) 1.2a 2001/02/26 changed application circuit(page 11) 1.3 2001/05/04 1. st7063 transition to ST7063C 2. moved qfp package dimensions page 12 to page 5 1.3a 2001/08/29 added substrate connect to vdd (page 4) 1.3b 2005/11/08 update temperature range
ST7063C v1.3b 2005/11/08 3/12 n functional block diagram segment driver segment driver bidirectional shifter(40bits) bidirectional shifter(40bits) data latch(40bits) data latch(40bits) contol v1 v2 v3 v4 cl2 cl1 m dl1shl1dr1dl2shl2dr2 v dd v ss v ee s1...............................s40s41...............................s80
ST7063C v1.3b 2005/11/08 4/12 n pad arrangement 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 9 6 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 3 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 s i z e : 3 8 0 0 x 2 6 0 0 m c o o r d i n a t e : c e n t e r m i n . p a d p i t c h : 1 2 0 m p a d s i z e : 9 0 x 9 0 m ( 0 , 0 ) c i r c l e h e r e t o f i n d t h e f i r s t p a d g 7 9 3 e " g 7 9 3 e " m a r k i n g : e a s y t o f i n d t h e p a d substrate connect to vdd.
ST7063C v1.3b 2005/11/08 5/12 n package dimensions
ST7063C v1.3b 2005/11/08 6/12 n pin configuration(qfp 100) s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s09 s08 s07 s06 s05 s04 s03 s02 s01 s70 s69 s68 s67 s66 s65 s64 s63 s62 s61 s60 s59 s58 s57 s56 s55 s54 s53 s52 s51 s50 s49 s48 s47 s46 s45 s44 s43 s42 s41 s 3 1 s 3 2 s 3 3 s 3 4 s 3 5 s 3 6 s 3 7 s 3 8 s 3 9 s 4 0 s 8 0 s 7 9 s 7 8 s 7 7 s 7 6 s 7 5 s 7 4 s 7 3 s 7 2 s 7 1 v e e v 1 v 2 v 3 v 4 v s s c l 1 s h l 1 s h l 2 n c n c v d d c l 2 d l 1 d r 1 d l 2 d r 2 m n c n c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 6 8 5 8 4 8 3 8 2 8 1 8 7 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 5 4 6 4 7 4 8 4 9 5 0 4 4
ST7063C v1.3b 2005/11/08 7/12 n pad name and coordinates pad no. pad name x y pad no. pad name x y pad no. pad name x y 1 s42 -1760 -1160 33 s74 1760 -780 65 s15 -180 1160 2 s43 -1630 -1160 34 s75 1760 -660 66 s14 -300 1160 3 s44 -1500 -1160 35 s76 1760 -540 67 s13 -420 1160 4 s45 -1380 -1160 36 s77 1760 -420 68 s12 -540 1160 5 s46 -1260 -1160 37 s78 1760 -300 69 s11 -660 1160 6 s47 -1140 -1160 38 s79 1760 -180 70 s10 -780 1160 7 s48 -1020 -1160 39 s80 1760 -60 71 s9 -900 1160 8 s49 -900 -1160 40 s40 1760 60 72 s8 -1020 1160 9 s50 -780 -1160 41 s39 1760 180 73 s7 -1140 1160 10 s51 -660 -1160 42 s38 1760 300 74 s6 -1260 1160 11 s52 -540 -1160 43 s37 1760 420 75 s5 -1380 1160 12 s53 -420 -1160 44 s36 1760 540 76 s4 -1500 1160 13 s54 -300 -1160 45 s35 1760 660 77 s3 -1630 1160 14 s55 -180 -1160 46 s34 1760 780 78 s2 -1760 1160 15 s56 -60 -1160 47 s33 1760 900 79 s1 -1760 1030 16 s57 60 -1160 48 s32 1760 1030 80 vee -1760 900 17 s58 180 -1160 49 s31 1760 1160 81 v1 -1760 780 18 s59 300 -1160 50 s30 1630 1160 82 v2 -1760 660 19 s60 420 -1160 51 s29 1500 1160 83 v3 -1760 540 20 s61 540 -1160 52 s28 1380 1160 84 v4 -1760 420 21 s62 660 -1160 53 s27 1260 1160 85 vss -1760 300 22 s63 780 -1160 54 s26 1140 1160 86 cl1 -1760 180 23 s64 900 -1160 55 s25 1020 1160 87 shl1 -1760 60 24 s65 1020 -1160 56 s24 900 1160 88 shl2 -1760 -60 25 s66 1140 -1160 57 s23 780 1160 89 vdd -1760 -180 26 s67 1260 -1160 58 s22 660 1160 90 cl2 -1760 -300 27 s68 1380 -1160 59 s21 540 1160 91 dl1 -1760 -420 28 s69 1500 -1160 60 s20 420 1160 92 dr1 -1760 -540 29 s70 1630 -1160 61 s19 300 1160 93 dl2 -1760 -660 30 s71 1760 -1160 62 s18 180 1160 94 dr2 -1760 -780 31 s72 1760 -1030 63 s17 60 1160 95 m -1760 -900 32 s73 1760 -900 64 s16 -60 1160 96 s41 -1760 -1030
ST7063C v1.3b 2005/11/08 8/12 n pin description pin name purpose description i/o vdd power for logic n/a vss ground for logic n/a vee lcd gnd for lcd driving voltage n/a v1 v2 lcd output used as select voltage level i v3 v4 lcd output used as non select voltage level i s1-s40 segment lcd driver output for part 1 o shl1 direction direction control for part 1 segments i dl1, dr1 data in /out if shl1 = 1 then dl1=out, dr1=in if shl1 = 0 then dl1=in, dr1=out i/o s41-s80 segment lcd driver output for part 2 o shl2 direction direction control for part 2 segments i dl2, dr2 data in/out if shl2 = 1 then dl2=out, dr2=in if shl2 = 0 then dl2=in, dr2=out i/o m alternation alternate the lcd driving waveform i cl1 latch clock latch the data after shift is completed i cl2 shift clock shift the data into the segments i
ST7063C v1.3b 2005/11/08 9/12 n functional description clock the cl1 is the clock to latch data on the falling edge. it latches the data input from the bi-directional shift register at the falling edge of cl1 and transfers its outputs to the lcd driver circuit. the cl2 is the clock to shift data on the falling edge. it shifts the serial data at the falling of cl2 and transfers the output of each bit of the register to the latch circuit. shift registers and data i/o the ST7063C supplies two sets of 40-bit shift register, which controls the shift direction by shl1 & shl2. the shl1 controls the 1st 40-bit shift register, and shl2 controls the 2nd 40-bit shift register. when shl1 is connected to vdd, the 1st shift direction is from s40 to s1; when shl1 is connected to vss, the shift direction changes from s1 to s40. when shl2 is connected to vdd, the 2nd shift direction is from s80 to s41; when shl2 is connected to vss, the shift direction changes from s41 to s80. the dl1, dr1, dl2, dr2 are data input or output option function. shift direction of channel 1 shl1 shift direction dl1 dr1 0 s1 s40 in out 1 s40 s1 out in shift direction of channel 2 shl2 shift direction dl2 dr2 0 s41 s80 in out 1 s80 s41 out in
ST7063C v1.3b 2005/11/08 10/12 n lcd output waveforms n timing characteristics output of latch (data) m output (s1 ~ s80) v1 v1 v2 v3 v4 v2 v3 v4 cl2 data in (dl1, dl2) (dr1, dr2) data out (dl1, dl2) (dr1, dr2) cl1 m v ih v il t r t wckh t f t wckl t dh t su t d v oh v ol t sl t ls t ls t wckh t r t su
ST7063C v1.3b 2005/11/08 11/12 n d.c characteristics symbol parameter test condition min. typ. max. unit applicable pin vdd operating voltage - 2.7 - 5.5 v - vlcd driver supply voltage vdd-vee 3 - 11 v - vih input high voltage - 0.7 vdd - vdd v vil input low voltage - 0 - 0.3 vdd v ilkg input leakage current vin =0 ~ vdd -5 - 5 ua cl1,cl2,m,shl1,shl 2 dl1,dl2,dr1,dr2 voh output high voltage ioh = -0.4ma vdd -0.4 - - v vol output low voltage iol = +0.4ma - - 0.4 v dl1,dl2,dr1,dr2 v1~v4, s1~s80 idd operating current fcl2 = 400khz - 100 300 ua vdd,vee iv leakage current vin =vdd ~ vee -10 - 10 ua v1 ~ v4 n a.c characteristics symbol parameter test condition min. max. unit applicable pin fcl data shift frequency - - 400 khz cl2 twckh clock high level width - 800 - ns cl1,cl2 twckl clock low level width - 800 - ns cl2 tsl clock set-up time cl2 cl1 500 - ns cl1,cl2 tls clock set-up time cl1 cl2 500 - ns cl1,cl2 tr/tf clock rise/fall time - - 200 ns cl1,cl2 tsu data set-up time - 300 - ns dl1,dl2,dr1,dr2 tdh data hold time - 300 - ns dl1,dl2,dr1,dr2 td data delay time cl = 15 pf - 500 ns dl1,dl2,dr1,dr2 n maximum absolute ratings symbol parameters min. max. unit vdd supply voltage -0.3 7 v topr operating temperature -30 85 tstg storage temperature -65 150
ST7063C v1.3b 2005/11/08 12/12 n application circuit : (2line x 40word) s t 7 0 6 6 u s t 7 0 6 3 c s t 7 0 6 3 c d o t m a t r i x l c d p a n e l - v o r g n d v c c ( + 5 v ) r e g s i s t e r r e g s i s t e r r e g s i s t e r r e g s i s t e r r e g s i s t e r v r d b 0 - d b 7 t o m p u v 5 v 4 v 3 v 2 v 1 m c l 1 c l 2 g n d v c c s e g 1 - 4 0 c o m 1 - 1 6 v e e v s s s h l 2 s h l 1 v d d d l 1 v 1 v 2 v 3 v 4 v 1 v 2 v 3 v 4 v e e v s s s h l 2 s h l 1 v d d d l 1 m c l 2 c l 1 d r 1 d l 2 d r 2 m c l 2 c l 1 d r 1 d l 2 d r 2 s e g 1 - 8 0 s e g 1 - 8 0 n o t e : r e g s i s t e r = 2 . 2 k ~ 1 0 k o h m v r = 1 0 k ~ 3 0 k o h m d

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